Author: Tom Kerrigan
Date: 16:03:54 02/28/03
Go up one level in this thread
>On February 26, 2003 at 12:03:42, Steve J wrote: > >> I've spent 25 years in manufacturing side of the semiconductor industry and >>would like to introduce what I call "No-Moore's Law". It describes the physical >>limitations that silicon (or any other compound) will run out of gas and can be >>shrunk no more. It also talks about some of the financial limitations of >>shrinking die. Some comments: 1) You can look at this like clock speed bounds. How many clock speeds have been declared as upper limits? I remember Microprocessor Report quoting a well-regarded microprocessor designer saying that 33MHz was the fastest a processor will ever run, because any faster and the mathematics for dealing with EM interference would be impossible to deal with. Well, advances in fab processes have taken care of that and now chips are running 100 times faster than that limit. 2) ... Similar to feature sizes. I hardly know anything about photolithography, but wasn't ~0.15um supposed to be some limit recently because any smaller and the wavelengths of light being used were simply too big to etch accurately? Apparently that problem has been licked too. I guess my point with these two comments is that new techniques have removed predicted barriers to smaller & faster semiconductors. While I won't argue that feature sizes will eventually be fractions of an atom's size, it seems possible that advances in manufacturing will remove one of the barriers you suggest, namely cost. Also speaking to cost, economy of scale seems to affect processors. It seems like the price of the average mainstream processor has been dropping like a rock over the past few years. You can get an Athlon 2000+ for $70 now, even though fabs have only been getting more expensive. The only explanation I can think of is that more people are buying more computers. That trend may keep up and offset the prices of new fab equipment. Advances in materials may be able to increase clock speeds even if feature sizes don't decrease. Low-k, SOI, whatnot. Same with design techniques. Apparently some automatic routing tools were used for Prescott that decreased clock skew across the entire chip to less than an inverter and routed some FP logic to shorten critical paths. Maybe tolerances in manufacturing and more advanced tools will enable things like wave pipelining and async logic on a broader basis. Anyway, I predict this stuff will get more interesting over the next decade, not less... -Tom
This page took 0 seconds to execute
Last modified: Thu, 15 Apr 21 08:11:13 -0700
Current Computer Chess Club Forums at Talkchess. This site by Sean Mintz.