Author: Keith Evans
Date: 15:56:07 04/09/03
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On April 09, 2003 at 18:38:56, Vincent Diepeveen wrote: >On April 09, 2003 at 17:21:18, Slater Wold wrote: > >>On April 09, 2003 at 16:34:23, Keith Evans wrote: >> >>>I couldn't seem to email you at the address in your profile. >> >>I moved/got married in the last few months. A lot has changed. A whole lot. >> >>I will correct it asap. >> >>>I wanted to ask if you were still pursuing that FPGA project, or potentially >>>would be if you had a knowledgable hardware guy to help out with the hardware >>>side of things. >> >>I actually did a LOT of studying for about 6 months on FPGAs and HDL. However I >>would never claim to know a whole lot, probably not even enough to make a >>legal-moving chess engine. >> >>But that's not what stopped me. Money did. Not only are the FPGAs expensive, >>but the software is just outrageous. Without a college/university connection, I >>just couldn't find a way to do it. > >it is very cheap. > >like $3000 for development board. another $2000 for 0.5mln gates and $10k or so >for a verilog compiler. > >compared with hardware asic design this is very cheap of course. > >>And one thing about me is, if I can't do it right, I won't do it. >> >>If you are offering your services (I know you have some connections), that would >>for sure probably be enough to spark enough interest to get this going again. You have to divide those Xilinx gate counts by a big factor depending on what you're doing. The board that I mentioned has 24 M gates if you go by the datasheet. Not cheap. I would probably divide that number by 6 or so... Even the numbers that you threw out are not exactly cheap. You need to buy the Xilinx ISE too since the webpack stuff won't handle decent sized parts.
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