Author: Gerd Isenberg
Date: 22:54:58 07/13/03
Go up one level in this thread
On July 13, 2003 at 18:33:51, Dieter Buerssner wrote: >On July 13, 2003 at 06:03:00, Gerd Isenberg wrote: > >>Why are the unsigned multiplications translated to "imul" by the compiler? > >Isn't it the same? You only use the lower 32 bits of the result (otherwise mul >would be needed). Imul gives the compiler much more freedom in register usage. > >Regards, >Dieter Hi Dieter, 1*1 or (-1)*1 and the lower 32 are different - or? Ok we interprete (-1) as 0xffffffff - i see. I didn't regocnize before, that there are more IMUL than MUL instructions. In Opposition to BSF (don't considering 64bit), the 32bit-IMUL seems to be further optimized with Opteron. Regards, Gerd Athlon: 1. The IMUL is a VectorPath instruction. It cannot be decoded or paired with other operations and, therefore, dispatches alone in pipe 0. The multiply latency is four cycles. IMUL reg16/32, mreg16/32, imm16/32 69h 11-xxx-xxx VectorPath 4/5 MUL mreg16 F7h 11-100-xxx VectorPath 4 MUL mreg32 F7h 11-100-xxx VectorPath 6 BSF reg16/32, mreg16/32 0Fh BCh 11-xxx-xxx VectorPath 8 Opteron: IMUL reg16, mreg16, imm16 69h 11-xxx-xxx VectorPath 4 IMUL reg32/64, mreg32/64, imm32 69h 11-xxx-xxx DirectPath 3/4 IMUL reg16/32/64, mreg16/32/64 0Fh AFh 11-xxx-xxx DirectPath 3/3/4 MUL mem16 F7h mm-100-xxx VectorPath 7 MUL mreg32 F7h 11-100-xxx Double 3 MUL mem32 F7h mm-100-xx Double 6 MUL mreg64 F7h 11-100-xxx Double 5 BSF reg16/32/64, mreg16/32/64 0Fh BCh 11-xxx-xxx VectorPath 8/8/9
This page took 0 seconds to execute
Last modified: Thu, 15 Apr 21 08:11:13 -0700
Current Computer Chess Club Forums at Talkchess. This site by Sean Mintz.