Author: Matt Taylor
Date: 14:45:21 07/20/03
Go up one level in this thread
On July 14, 2003 at 16:07:27, Robert Hyatt wrote: >On July 14, 2003 at 15:33:37, Gerd Isenberg wrote: > <snip> >>puhh... that's about 1/2 microsecond. I remember the days with >>2MHz - 8085 or Z80 CPU - can't beleave it. A few questions... > > > >Don't believe it because it is _wrong_. Run "lm-bench" on your computer. >It will very accurately measure random access latency. The slowest I have >seen is 150ns on my dual, using registered DDRAM. My laptop uses SDRAM and >clocks in around 120ns. My quad xeons are all around 125ns. > >I've not seen any 400+ ns numbers although it is very possible that rambus >might be that slow on latency, although it is very fast on bandwidth. I would add that my dual-Athlon runs at 130ns with registered DDR SDRAM. Using lmbench my AthlonXP showed latencies as low as 100ns on a 166 MHz FSB. When I used pc2100 (133 MHz) with my AthlonXP 2500 (166 MHz FSB), I saw latencies as high as 200ns (the FSB is no longer running in lock-step with the memory bus). I find it difficult to believe that RDRAM latency would be as high as 400ns. As I recall, RDRAM is about 50% slower in latency, and 50% slower than my worst-case figure is only 300ns. More likely it is 50% slower than my average-case figure (100ns) which would make it about 190ns after adjusting for the difference in bus speed. >>I'm not familar with dual-architectures. Is it a kind of shared memory via >>pci-bus? How do you access such ram - are the some alloc like api-functions? >>What happens, if one perocessor writes this memory through cache - what about >>possible cache copies of this address in the other processor, or in general how >>do the severel processor caches syncronise? >>I guess each processor has it's own local main-memory. >> > > > >No. Each processor sits on the same bus with memory. So both can access >it independently. However, cache coherency is a problem, but in the Intel >world it is handled by some clever cache design so that the cache controllers >are aware of what is being done by the "other cache" and knows when the other >cache modifies a value that is in the local cache. It's messy, but it works. > >Caches still use write-back update policy so that memory is not updated until >the cache line (Modified cache line) is about to be overwritten. However, if >two caches have the same cache line (memory addresses) and one modifies any of >the cache line, the other invalidates its copy so the next read will refresh >things correctly. MESI protocol is fairly standard, isn't it? The Athlon has used it for the several years it's been available, and I think the implementation itself was borrowed from the Alpha which goes back even further. <snip> >>1.) if data is already in 1. level cache > >This is a one-cycle deal. <snip> No, this is 2 clocks on P4 and 3 clocks on Athlon. I've never seen Intel quote the P4 figure, but a Google search will turn up dozens of references from websites like arstechnica which quote that figure. -Matt
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