Author: Keith Evans
Date: 16:00:25 09/20/02
Go up one level in this thread
On September 20, 2002 at 16:59:14, Robert Hyatt wrote: >On September 20, 2002 at 00:30:39, Keith Evans wrote: > >>On September 19, 2002 at 22:19:14, Keith Evans wrote: >> >>>On September 19, 2002 at 21:01:37, Ian Osgood wrote: >>> >>>>> I'm still trying to keep memory usage small >>>>> in the hope to port this someday to the F25 >>>>> asynchronous Forth multiprocessor >>>>> [2 ps per instruction, 25 CPUs per die]. ) >>>> >>>>Actually, the chip is called the 25x, and has 0.3ns per instruction, 1ns memory >>>>access, 2400 MIPS peak. >>>> >>>>Ian >>> >>>1 ns memory access to what memory? A very small on-chip memory? What performance >>>will you get to off-chip memory? How much off-chip memory is supported? What >>>types of off-chip memory are supported? >>> >>>Also how deep are the stacks on the 25x? What happens when you fill them up? >>> >>>(As far as I know there are no plans to actually build the 25x.) >>> >>>Keith >> >>As far as I could tell from google: >> >>Neither the x25, or the X18 has actually been built. (I personally doubt that >>they ever will be built. It would be interesting to hear what happened at iTv.) >> >>The X18 was quoted to have: >> >>2 16-deep push-down stacks >>128 words ROM, 384 DRAM >>256K words of external memory with 4 ns (250 MHz) access - cache memory chip >> > > >Some of that doesn't make sense. IE there is _no_ way to read from DRAM in >4 nanoseconds. Yes the memory bus can run that fast. New intel machines >are running the bus at > 500mhz, but that does not translate into 2 ns >accesses. It translates into _many_ cycles of waiting to get the data... I believe that it was referring to some type of SRAM chip. I'm skeptical too - those guys make a lot of wild claims. (I don't want to start ranting about that here. Don't get me started on OKAD...) > > > > > >>All off-chip accesses appear to be done via software bit banging
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