Author: Vincent Diepeveen
Date: 15:53:14 04/09/03
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On April 09, 2003 at 17:49:37, Keith Evans wrote: >On April 09, 2003 at 17:21:18, Slater Wold wrote: > >>On April 09, 2003 at 16:34:23, Keith Evans wrote: >> >>>I couldn't seem to email you at the address in your profile. >> >>I moved/got married in the last few months. A lot has changed. A whole lot. >> >>I will correct it asap. >> >>>I wanted to ask if you were still pursuing that FPGA project, or potentially >>>would be if you had a knowledgable hardware guy to help out with the hardware >>>side of things. >> >>I actually did a LOT of studying for about 6 months on FPGAs and HDL. However I >>would never claim to know a whole lot, probably not even enough to make a >>legal-moving chess engine. >> >>But that's not what stopped me. Money did. Not only are the FPGAs expensive, >>but the software is just outrageous. Without a college/university connection, I >>just couldn't find a way to do it. >> >>And one thing about me is, if I can't do it right, I won't do it. >> >>If you are offering your services (I know you have some connections), that would >>for sure probably be enough to spark enough interest to get this going again. > >I thought that the cost might get to you. I may be able to get some basically >old (not powerful enough) stuff at work, but it will take a little while before >I'll know anything. The cool thing is that the FPGAs are loaded from CF, so I >could email new hardware to you, and you wouldn't need anything other than a $20 >(or whatever) standard CF reader on your PC. > >AFAIK this platform is more powerful than the stuff that Chrilly is using, but >it would need to talk to the host over a serial port instead of PCI. You could >ultimately fit a whole engine including big hash tables on it, so I don't think >that the serial port would be a bottleneck. I would just have the PC handle the >opening book and interface to Winboard/whatever. (There are 6 XC2V4000 parts on >it if that means anything to you. Plus there are two DIMM sockets. Nope this >wasn't powerful enough for us...) > >One of the things that keeps me from doing a project like this, is the knowledge >that it would require a lot of software work to tune it, and a lot of brain >power to analyze its performance. So I could focus on hardware and let you write >software, test it, suggest features in English rather than writing them in >Verilog. > >Anyhow I'll need some time before I would know for sure and get you involved, >but I just wanted to see if you still had any interest. > >Regards, >Keith i would right away create a version of diep in fpga if i was convinced that the fpga cards can keep up in speed with software. diep gets tested at icc and fics. icc is done by Zeke Smigel. He lives somewhere in USA. FICS by Ralph Joerg Hellmig. He teaches in germany. Don't they all need to get shipped by me a hardware card each time? Is there *any* way i can update them by email a new version? That's one speed part. second speed part is how many Mhz can we clock these things? I remember when Chrilly started. He didn't tell it but looking back. He could get it to 25-30Mhz then or so (like 33Mhz for a day of synthesizing). It is 2003 now. End of 2003 he might get the latest cards which get him 2 times faster perhaps. So like 50Mhz or so. Most of that 2 times faster is simply software improvements. So it needs like 4 years to get the FPGA to double in speed. Then each 'compile' takes hours and hours and hours. Even a very fast machine with a lot of RAM isn't speeding up synthesizing. Imagine that i write bugfree code right away? No way. If i try to improve something. you need like 10 recompiles. At least i do. Right now i modify something in parallellism of diep. ok that's SMP modification. that's just software of course. hardware development is very very primitive. Of course the speedup is huge. DIEP gets at a fast dual K7 like 200+ k nps now. my old thing delivers like 130k nps. so at 3.2Ghz it is like 130-150k nps Each node costs therefore on average like 3.2G / 0.15M = 21333 clocks. Chrilly managed now if i remember well like 8 clocks a node. That means that the coming 4 years or so at say 50Mhz he'll get 50 / 8 = 6MLN nps. Very good of course. However you lose a lot because of not being capable of using hashtables and the move ordering is a lot more poor than in software of course. So you lose a factor 4 directly. still 1.25MLN nps. latest K7s deliver 200k+ nps now. Please explain to me why a cheap 4 processor opteron in 4 years of time won't get 1.25MLN nps either! a) more registers b) bigger caches and faster caches (so relatively seen diep profits more than other programs from newer CPUs) Now please imagine that this is for *diep*. Brutus would probably need when it was written in software like 6000 clocks a node at most. At least a factor 3 faster. Clearly its advantage is when they can SELL a 50Mhz version of it with the WORLDCHAMPS Version (so not something with less gates than what it uses up now) end of 2003. Start of 2004 when brutus would be in software it would effectively be already same speed. Best regards, Vincent
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